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3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 X 16,384 CHANNELS
IDT72V73263
FEATURES:
* * * * * * * * * * * * * * *
* * * *
Up to 64 serial input and output streams Maximum 16,384 x 16,384 channel non-blocking switching Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, 16.384Mb/s or 32.768Mb/s Rate matching capability: rate selectable on both RX and TX in eight groups of 8 streams Optional Output Enable Indication Pins for external driver High-Z control Per-channel Variable Delay Mode for low-latency applications Per-channel Constant Delay Mode for frame integrity applications Enhanced Block programming capabilities TX/RX Internal Bypass Automatic identification of ST-BUS and GCI serial streams Per-stream frame delay offset programming Per-channel High-Impedance output control Per-channel processor mode to allow microprocessor writes to TX streams Bit Error Rate Testing (BERT) for testing Direct microprocessor access to all internal memories
Selectable Synchronous and Asynchronous Microprocessor bus timing modes IEEE-1149.1 (JTAG) Test Port Available in 208-pin (28mm x 28mm) Plastic Quad Flatpack (PQFP) and 208-pin (17mm x 17mm) Plastic Ball Grid Array (PBGA) Operating Temperature Range -40C to +85C
DESCRIPTION:
The IDT72V73263 has a non-blocking switch capacity of 16,384 x 16,384 channels at 32.768Mb/s. With 64 inputs and 64 outputs, programmable per stream control, and a variety of operating modes the IDT72V73263 is designed for the TDM time slot interchange function in either voice or data applications. Some of the main features of the IDT72V73263 are LOW power 3.3 Volt operation, automatic ST-BUS(R) /GCI sensing, memory block programming, simple microprocessor interface , JTAG Test Access Port (TAP) and per stream programmable input offset delay, variable or constant throughput modes, output enable and processor mode, BER testing, bypass mode, and advanced block programming.
FUNCTIONAL BLOCK DIAGRAM
RESET
VCC
GND
ODE
RX0-7 RX8-15 RX16-23 RX24-31 RX32-39 RX40-47 RX48-55 RX56-63
TX0-TX7
Data Memory
MUX
TX8-15/OEI0-7 TX16-23
Receive Serial Data Streams Internal Registers Connection Memory
Transmit Serial Data Streams
TX24-31/OEI16-23 TX32-39 TX40-47/OEI32-39 TX48-55 TX56-63/OEI48-55
Timing Unit
Microprocessor Interface
JTAG Port
C32i
F32i
S/A DS CS R/W A0-A15 BEL DTA/ D0-D15 BEH
TMS TDI TCK TDO TRST 6160 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.
OCTOBER 2003
DSC-6160/3
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
*
GND C32i F32i Vcc S/A(1) TMS TDI TDO TCK TRST DS CS R/W VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BEL DTA/BEH D15 D14 D13 D12 VCC GND D11 D10 D9 D8 VCC GND D7 D6 D5 D4 VCC GND D3 D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
RESET ODE RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 TX0 TX1 TX2 TX3 VCC GND TX4 TX5 TX6 TX7 VCC GND TX8/OEI0 TX9/OEI1 TX10/OEI2 TX11/OEI3 VCC GND TX12/OEI4 TX13/OEI5 TX14/OEI6 TX15/OEI7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 RX17 RX18 RX19 RX20 RX21 RX22 RX23 TX16 TX17 TX18 TX19
PIN 1
D1 D0 RX63 RX62 RX61 RX60 RX59 RX58 RX57 RX56 TX63/OEI55 TX62/OEI54 TX61/OEI53 TX60/OEI52 VCC GND TX59/OEI51 TX58/OEI50 TX57/OEI49 TX56/OEI48 VCC GND TX55 TX54 TX53 TX52 VCC GND TX51 TX50 TX49 TX48 RX55 RX54 RX53 RX52 RX51 RX50 RX49 RX48 RX47 RX46 RX45 RX44 RX43 RX42 RX41 RX40 TX47/OEI39 TX46/OEI38 TX45/OEI37 TX44/OEI36
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VCC GND TX20 TX21 TX22 TX23 VCC GND TX24/OEI16 TX25/OEI17 TX26/OEI18 TX27/OEI19 VCC GND TX28/OEI20 TX29/OEI21 TX30/OEI22 TX31/OEI23 RX24 RX25 RX26 RX27 RX28 RX29 RX30 RX31 RX32 RX33 RX34 RX35 RX36 RX37 RX38 RX39 TX32 TX33 TX34 TX35 GND VCC TX36 TX37 TX38 TX39 GND VCC TX40/OEI32 TX41/OEI33 TX42/OEI34 TX43/OEI35 GND VCC
6160 drw02
NOTE: 1. S/A should be tied directly to VCC or GND for proper operation.
PQFP: 0.50mm pitch, (28mm x 28mm) (DR208-1 order code: DR) TOP VIEW
2
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONTINUED)
A1 BALL PAD CORNER
A
C32i RESET ODE RX1 RX4 TX0 TX4 TX7 TX12/ OEI4 TX11/ OEI3 TX10/ OEI2 VCC TX15/ OEI7 TX14/ OEI6 TX13/ OEI5 VCC RX11 RX15 RX20 TX16 TX18 TX19
B
F32i Vcc RX0 RX2 RX5 TX1 TX5 TX8/ OEI0 TX9/ OEI1 VCC RX10 RX14 RX19 RX23 TX17 TX20
C
S/A(1) TMS TDI RX3 RX6 TX2 TX6 RX9 RX13 RX18 RX22 TX22 TX21
D
TDO TCK TRST DS RX7 TX3 VCC RX8 RX12 RX17 RX21 TX24/ OEI16 TX26/ OEI18 TX29/ OEI21 RX25 TX23
E
CS R/W A0 A1 RX16 TX27/ OEI19 TX30/ OEI22 RX26 TX25/ OEI17 TX28/ OEI20 RX24
F
A2 A3 A4 A5 TX31/ OEI23 GND GND GND GND VCC
G
A6 A7 A8 VCC
H
A9 A10 A11 VCC GND GND GND GND VCC RX29 RX28 RX27
J
A14 A13 A12 VCC GND GND GND GND VCC RX30 RX31 RX32
K
D15 DTA/ BEH D13 A15 VCC GND GND GND GND VCC RX33 RX34 RX35
L
D12 D14 BEL RX36 RX37 RX38 RX39
M
D8 D9 D10 D11 TX32 TX33 TX34 TX35
N
D5 D6 D7 RX56 TX60/ OEI52 TX61/ OEI53 TX62/ OEI54 TX63/ OEI55 TX56/ OEI48 TX57/ OEI49 TX58/ OEI50 TX59/ OEI51 VCC VCC VCC VCC RX51 RX47 TX36 TX37 TX38 TX39
P
D3 D4 RX60 RX57 TX53 TX50 TX49 RX54 RX50 RX46 RX43 TX40/ OEI32 RX40 TX41/ OE33 TX46/ OEI38 TX45/ OEI37 TX42/ OEI34 TX43/ OEI35 TX44/ OEI36
R
D2 RX63 RX61 RX58 TX54 TX51 TX48 RX53 RX49 RX45 RX42
T
D1 D0 RX62 RX59 TX55 TX52 RX55 RX52 RX48 RX44 RX41 TX47/ OEI39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6160 drw03
NOTE: 1. S/A should be tied directly to VCC or GND for proper operation.
PBGA: 1mm pitch, 17mm x 17mm (BB208-1 order code: BB) TOP VIEW
3
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL A0-A15 BEL C32i CS D0-15 DS DTA/BEH NAME Address 0-15 Byte Enable LOW Clock Chip Select Data Bus 0-15 Data Strobe Data Transfer Acknowledgment Active LOW Output I/O I I I I I/O I I/O PQFP PIN NO. *See PQFP Table Below 31 2 12 *See PQFP Table Below 11 D4 32 K2 PBGA PIN NO. *See PBGA Table Below L4 A1 E1 *See PBGA Table Below DESCRIPTION These address lines access all internal memories. In synchronous mode, this input will enable the lower byte (D0-7) on to the data bus. Serial clock for shifting data in/out on the serial data streams. This input accepts a 32.768MHz clock. Active LOW input used by a microprocessor to activate the microprocessor port of the device. These pins are the data bus of the microprocessor port. This active LOW input works in conjunction with CS to enable the read and write operations. This active LOW input sets the data bus lines (D0-D15). In asynchronous mode this pin indicates that a data bus transfer is complete. When the bus cycle ends,this pin drives HIGH and then High-Z allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is High-Z. When the device is in /Byte Enable HIGH synchronous bus mode, this pin acts as an input and will enable the upper byte (D8-15) on to the data bus. This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS and GCI specifications. Ground. This is the output enable control for the TX serial outputs. When ODE input is LOW and the OSB bit of the CR register is LOW, all TX outputs are in a High-Impedance state. If this input is HIGH, the TX output drivers are enabled. However, each channel may still be put into a High-Impedance state by using the per channel control bits in the Connection Memory HIGH. Serial data Input Stream. These streams may have data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, 16.384Mb/s, or 32.768Mb/s depending upon the selection in Receive Data Rate Selection Register (RDRSR). This input (active LOW) puts the device in its reset state that clears the device internal counters, registers and brings TX0-63 and microport data outputs to a High-Impedance state. The RESET pin must be held LOW for a minimum of 20ns to reset the device. This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. This input will select between asynchronous microprocessor bus timing and synchronous microprocessor bus timing. In synchronous mode, DTA/BEH acts as the BEH input and is used in conjunction with BEL to output data on the data bus. In asynchronous bus mode, BEL is tied LOW and DTA/BEH acts as the DTA, data bus acknowledgment output. Provides the clock to the JTAG test logic. JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up when not driven. JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in High-Impedance state when JTAG scan is not enabled. JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-up when not driven. Asynchronously initializes the JTAG TAP controller by putting it in the Test-LogicReset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure that the device is in the normal functional mode.
F32i GND ODE
Frame Pulse
I
3 *See PQFP Table Below
B1 *See PBGA Table Below A3
Output Drive Enable
I
207
RX0-63
RX Input 0 to 63
I
*See PQFP Table Below 208
*See PBGA Table Below A2
RESET
Device Reset:
I
R/W S/A
Read/Write Synchronous/ Asynchronous Bus Mode Test Clock Test Serial Data In Test Serial Data Out Test Mode Select Test Reset
I I
13 5
E2 C1
TCK TDI TDO TMS TRST
I I O I I
9 7 8 6 10
D2 C3 D1 C2 D3
4
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
SYMBOL TX0-7 TX16-23 TX32-39 TX48-55 NAME TX Output I/O O PQFP PIN NO. *See PQFP Table Below PBGA PIN NO. *See PBGA Table Below DESCRIPTION Serial data Output Stream. These streams may have data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s,16.384Mb/s, or 32.768Mb/s depending upon the selection in Transmit Data Rate Selection Register (TDRSR). If G0/G2/G4/G6 are programmed to 32.768Mb/s mode the corresponding odd group is unavailable (G1/G3/G5G7). When output streams are selected via TDRSR, these pins are the TX output streams. When output enable indication function is selected, these pins reflect the active or HighImpedance status for the corresponding TX output stream. +3.3 Volt Power Supply.
TX8-15/OEI0-7 TX Output /Output TX24-31/OEI16-23 Enable Indication TX40-47/OEI32-39 TX56-63/OEI48-55 VCC
O
*See PQFP Table Below
*See PBGA Table Below
*See PQFP Table Below
*See PBGA Table Below
PQFP PIN NUMBER TABLE
SYMBOL A0-A15 D0-D15 GND RX0-63 NAME Address A0-15 Data Bus 0-15 Ground RX Input 0 to 63 I I/O I I/O PIN NUMBER 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30. 54, 53, 52, 51, 48, 47, 46, 45, 42, 41, 40, 39, 36, 35, 34, 33. 1, 38, 44, 50, 68, 74, 80, 106, 112, 118, 143, 149, 155, 181, 187, 193. 206, 205, 204, 203, 202, 201, 200, 199, 176, 175, 174, 173, 172, 171, 170, 169, 168, 167, 166, 165, 164, 163,162 ,161, 138, 137, 136, 135, 134, 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, 123, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 62, 61, 60, 59, 58, 57, 56, 55. 198, 197, 196, 195, 192, 191, 190, 189, 160, 159, 158, 157, 154, 153, 152, 151 122, 121, 120, 119, 116, 115, 114, 113 84, 83, 82, 81. 78, 77, 76, 75 186, 185, 184, 183, 180, 179, 178,177. 148, 147, 146, 145, 142, 141, 140, 139. 110, 109, 108, 107, 104, 103, 102, 101. 72, 71, 70, 69, 66, 65, 64, 63. 4, 14, 37, 43, 49, 67, 73, 79, 105, 111, 117, 144, 150, 156, 182, 188, 194.
TX0-TX7 TX16-23 TX32-39 TX48-55
TX Output
O
TX8-15/OEI0-7 TX Output/Output TX24-31/OEI16-23 TX40-47/OEI32-39 TX56-63/OEI48-55 Vcc
O
PBGA PIN NUMBER TABLE
SYMBOL A0-A15 D0-D15 GND RX0-63 NAME Address A0-15 Data Bus 0-15 Ground RX Input 0 to 63 I I/O I I/O PIN NUMBER E3, E4, F1, F2, F3, F4, G1, G2, G3, H1, H2, H3, J3, J2, J1, K3. T2, T1, R1, P1, P2, N1, N2, N3, M1, M2, M3, M4, L1, L2, L3, K1. G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10,K7, K8, K9, K10, B3, A4, B4, C4, A5, B5, C5, D5, D11, C11, B11, A11, D12, C12, B12, A12, E13, D13, C13, B13, A13, D14, C14 , B14, G16, G15, G14, H16, H15, H14, J14, J15, J16, K14, K15, K16, L13, L14, L15, L16, R14, T13, R13, P13, T12, R12, P12, N12, T11, R11, P11, N11, T10, R10, P10, T9, N4, P4, R4, T4, P3, R3, T3, R2. A6, B6, C6, D6, A7, B7, C7, A8 A14, B15, A15, A16, B16, C16, C15, D16 M13, M14, M15, M16, N13, N14, N15, N16 R9, P9, P8, R8. T8, P7, R7, T7 B8, C8, C9, B9, A9, C10, B10, A10. D15, E16, E15, E14, F16, F15, F14, F13. P14, P15, P16, R16, T16, T15, R15, T14. N6, P6, R6, T6, N5, P5, R5, T5. B2, D7, D8, D9, D10, G4, G13, H4, H13, J4, J13, K4, K13, N7, N8, N9, N10.
TX0-TX7 TX16-23 TX32-39 TX48-55
TX Output
O
TX8-15/OEI0-7 TX Output/Output TX24-31/OEI16-23 TX40-47/OEI32-39 TX56-63/OEI48-55 Vcc
O
5
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED):
The IDT72V73263 is capable of switching up to 16,384 x 16,384 channels without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per-channel basis. The 64 serial input streams (RX) of the IDT72V73263 can be run at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, 16.384Mb/s or 32.768Mb/s allowing 32, 64, 128, 256 or 512 channels per 125s frame. The data rates on the output streams can independently be programmed to run at any of these data rates. With two main operating modes, Processor Mode and Connection Mode, the IDT72V73263 can easily switch data from incoming serial streams (Data Memory) or from the controlling microprocessor via Connection Memory. As control and status information is critical in data transmission, the Processor Mode is especially useful when there are multiple devices sharing the input and output streams. With data coming from multiple sources and through different paths, data entering the device is often delayed. To handle this problem, the IDT72V73263 has a Frame Offset feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +7.5 clock cycles. The IDT72V73263 also provides a JTAG test access port, memory block programming, Group Block Programming, RX/TX internal bypass, a simple microprocessor interface and automatic ST-BUS /GCI sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities.
MOD2-0 bits are set to 0-0-1 accordingly, that particular channel will be in Constant Delay Mode. Finally, if the MOD2-0 bits are set to 0-0-0, that particular channel will be in Variable Delay Mode. SERIAL DATA INTERFACE TIMING The master clock frequency of the IDT72V73263 is 32.768MHz, C32i. For 32.768Mb/s data rates, this results in a single-bit per clock. For 16.384Mb/s, 8.192Mb/s, 4.096Mb/s, and 2.048Mb/s this will result in two, four, eight, and sixteen clocks per bit, respectively. The IDT72V73263 provides two different interface timing modes, ST-BUS or GCI. The IDT72V73263 automatically detects the polarity of an input frame pulse and identifies it as either ST-BUS or GCI. For 32.768Mb/s, in ST-BUS Mode, data is clocked out on a falling edge and is clocked in on the subsequent rising-edge. For 16.384Mb/s, 8.192Mb/s, 4.096Mb/s, and 2.048Mb/s however there is not the typical associated clock since the IDT72V73263 accepts only a 32.768MHz clock. As a result there will be 2, 4, 8, and 16 clock between the 32.768Mb/s transmit edge and the subsequently transmit edges. Although in this is the case, the IDT72V73263 will appropriately transmit and sample on the proper edge as if the respective clock were present. See ST-BUS Timing for detail. For 32.768Mb/s, in GCI Mode, data is clocked out on a rising edge and is clocked in on the subsequent falling-edge. For 16.384Mb/s, 8.192Mb/s, 4.096Mb/s, and 2.048Mb/s however, again there is not the typical associated clock since the IDT72V73263 accepts only a 32.768MHz clock. As a result there will 2, 4, 8, and 16 clocks between the 32.768Mb/s transmit edge and the other transmit edges. Although this is the case, the IDT72V73263 will appropriately transmit and sample on the proper edge as if the respective clock were present. See GCI Bus Timing for detail. DELAY THROUGH THE IDT72V73263 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, variable throughput delay is best as it ensure minimum delay between input and output data. In wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. The delay through the device varies according to the type of throughput delay selected in the MOD bits of the Connection Memory. VARIABLE DELAY MODE (MOD2-0 = 0-0-0) In this mode, mostly for voice applications where minimum throughput delay is desired, delay is dependent on the combination of source and destination channels. The minimum delay achievable is a 3 channel periods of the slower data rate. CONSTANT DELAY MODE (MOD2-0 = 0-0-1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the IDT72V73263, the minimum throughput delay achievable in Constant Delay mode will be one frame plus one channel. See Table 14.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY All data that comes in through the RX inputs go through a serial-to-parallel conversion before being stored into internal Data Memory. The 8.192 KHz frame pulse (F32i) is used to mark the 125s frame boundaries and to sequentially address the input channels in Data Memory. Data output on the TX streams may come from either the serial input streams (Data Memory) or from the Connection Memory via the microprocessor or in the case that RX input data is to be output, the addresses in Connection Memory are used to specify a stream and channel of the input. The Connection Memory is setup in such a way that each location corresponds to an output channel for each particular stream. In that way, more than one channel can output the same data. In Processor Mode, the microprocessor writes data to the Connection Memory locations corresponding to the stream and channel that is to be output. The lower half (8 least significant bits) of the Connection Memory LOW is output every frame until the microprocessor changes the data or mode of the channels. By using this Processor Mode capability, the microprocessor can access input and output time-slots on a per-channel basis. The three least significant bits of the Connection Memory HIGH are used to control per-channel mode of the output streams. The MOD2-0 bits are used to select Processor Mode, Constant or Variable Delay Mode, Bit Error Rate, and the High-Impedance state of output drivers. If the MOD2-0 bits are set to 1-1-1 accordingly, only that particular output channel (8 bits) will be in the HighImpedance state. If the MOD2-0 bits are set to 1-0-0 accordingly, that particular channel will be in Processor Mode. If the MOD2-0 bits are set to 1-0-1 a Bit Error Rate Test pattern will be transmitted for that time slot. See BERT section. If the
6
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
MICROPROCESSOR INTERFACE The IDT72V73263's microprocessor interface looks like a standard RAM interface to improve integration into a system. With a 16-bit address bus and a 16-bit data bus all memories can be accessed. Using the TSI microprocessor interface, reads and writes are mapped into Data and Connection memories. By allowing the internal memories to be randomly accessed, the controlling microprocessor has more time to manage other peripheral devices and can more easily and quickly gather information and setup the switch paths. Table 1 shows the mapping of the addresses into internal memory blocks. In order to minimize the amount of memory mapped space however, the Memory Select (MS1-0) bits in the Control Register must be written to first to select between the Connection Memory HIGH, the Connection Memory LOW, or Data Memory. Effectively, the Memory Select bits act as an internal mux to select between the Data Memory, Connection Memory HIGH, and Connection Memory LOW. MEMORY MAPPING The address bus on the microprocessor interface selects the internal registers and memories of the IDT72V73263. The most significant bit of the address select between the registers and internal memories. See Table 1 for mappings. As explained in the Initialization section, after system power-up, the TDRSR and RDRSR, should be programmed immediately to establish the desired switching configuration. The data in the Control Register consists of the Software Reset, RX/TX Bypass, Output Enable Polarity, All Output Enable, Full Block Programming, Block Programming Data, Begin Block Programming Enable, Reset Connection Memory LOW in Block Programming, Output Standby, and Memory Select. SOFTWARE RESET The Software Reset serves the same function as the hardware reset. As with the hard reset, the Software Reset must also be set HIGH for 20ns before bringing the Software Reset LOW again for normal operation. Once the Software Reset is LOW, internal registers and other memories may be read or written. During Software Reset, the microprocessor port is still able to read from all
internal memories. The only write operation allowed during a Software Reset is to the Software Reset bit in the Control Register to complete the Software Reset. CONNECTION MEMORY CONTROL If the ODE pin and the Output Standby bit are LOW, all output channels will be in three-state. See Table 2 for detail. If MOD2-0 of the Connection Memory HIGH is 1-0-0 accordingly, the output channel will be in Processor Mode. In this case the lower eight bits of the Connection Memory LOW are output each frame until the MOD2-0 bits are changed. If MOD2-0 of the Connection Memory HIGH are 0-0-1 accordingly, the channel will be in Constant Delay Mode and bits 14-0 are used to address a location in Data Memory. If MOD2-0 of the Connection Memory HIGH are 0-0-0, the channel will be in Variable Delay Mode and bits 14-0 are used to address a location in Data Memory. If MOD2-0 of the Connection Memory HIGH are 1-1-1, the channel will be in High-Impedance mode and that channel will be in three-state. RX/TX INTERNAL BYPASS When the Bypass bit of control registers is 1, all RX streams will be "shorted" to TX in effect bypassing all internal circuitry of the TSI. This effectively sets the TSI to a 1-to-1 switch mode with minimal I/O delay. A zero can be written to allow normal operation. The intention of this mode is to minimize the delay from the RX input to the TX output making the TSI "invisible". INITIALIZATION OF THE IDT72V73263 After power up, the state of the Connection Memory is unknown. As such, the outputs should be put in High-Impedance by holding the ODE pin LOW. While the ODE is LOW, the microprocessor can initialize the device by using the Block Programming feature and program the active paths via the microprocessor bus. Once the device is configured, the ODE pin (or Output Standby bit depending on initialization) can be switched to enable the TSI switch.
7
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 1 -- ADDRESS MAPPING
A15 1 A14 A13 A12 A11 A10 A9 A8 CH8 A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W Location Hex Value STA5 STA4 STA3 STA2 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Internal 0x8000memory 0xFFFF (CM, DM (read only)(1) Control TDRSR0 TDRSR1 RDRSR0 RDRSR1 BPSA BPEA BIS BER FOR0 FOR1 FOR2 FOR3 FOR4 FOR5 FOR6 FOR7 FOR8 FOR9 FOR10 FOR11 FOR12 FOR13 FOR14 FOR15 0x00XX Register 0x02XX 0x04XX 0x06XX 0x08XX 0x0AXX 0x0CXX 0x-0EXX 0x10XX 0x20XX 0x22XX 0x24XX 0x26XX 0x28XX 0x2AXX 0x2CXX 0x2EXX 0x30XX 0x32XX 0x34XX 0x36XX 0x38XX 0x3AXX 0x3CXX 0x3EXX
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X X X X X X X X X X X
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
NOTE: 1) Select Connection Memory High, Connection Memory Low, or Data Memory by setting the MS1-0 bits in the Control Register.
TABLE 2 OUTPUT HIGH-IMPEDANCE CONTROL
MOD2-0 BITS IN CONNECTION MEMORY HIGH 1-1-1 Any, other than 1-1-1 Any, other than 1-1-1 Any, other than 1-1-1 Any, other than 1-1-1 Any, other than 1-1-1
NOTE: X = Don't Care.
OE X BIT OF TDRSR CONTROL REGISTER 1 1 1 1 1 0
ODE PIN
OSB BIT IN
OUTPUT DRIVER STATUS
X 0 0 1 1 X
X 0 1 0 1 X
Per Channel High-Impedance All TX in High-Impedance Enable Enable Enable Group x of OEx is in High-Impedance
8
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 3 CONTROL REGISTER (CR) BITS
Reset Value:
15 SRS 14 BYP
0000H
13 OEPOL 12 AOE 11 PRST 10 CBER 9 SBER 8 FBP 7 BPD2 6 BPD1 5 BPD0 4 BPE 3 RCML 2 OSB 1 MS1 0 MS0
BIT 15 14
NAME SRS (Software Reset) BYP (RX/TX Bypass)
DESCRIPTION A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation. When the Bypass bit is 1, all RX streams will be "shorted" to TX--in effect bypassing all internal circuitry of the TSI. This effectively sets the TSI to a 1-to-1 switch mode with almost only a few nanoseconds of delay. A zero can be written to allow normal operation. The intention of this mode is to minimize the delay from the RX input to the TX output making the TSI "invisible". Any offset values in the FOR register will be required. When 1, a one on OEI pin denotes an active state on the output data stream; zero on OEI pin denotes High-Impedance state. When 0, a one denotes High-Impedance and a zero denotes an active state. OEI mode is entered on a per-group basis in the DRSR. When 1, all output stream pins (TXn) become OEI to allow for a two-chip solution for a larger switching matrix with OEI pins. When in AOE the DRS must be set to the corresponding data rate of the other device. When HIGH, the PRBS transmitter output will be initialized. A low to high transititon of this bit clears the BER register (BERR). A low to high transition in this bit starts the bit error rate test. The bit error test results is kept in the BER register (BERR). When 1, this bit overrides the BPSA and BPEA registers and programs the full Connection Memory space. When 0, the BPSA and BPEA determine the Connection Memory space to be programmed.
13 12 11 10 9 8 7-5
OEPOL (Output Enable Polarity) AOE (All Output Enable) PRST (PRBS Reset) CBER (Clear Bit Error Rate) SBER (Start Bit Error Rate) FBP (Full Block Programming)
BPD2-0 These bits carry the value to be loaded into the Connection Memory block whenever the Connection Memory block programming (Block Programming Data) features is activated. After the BPE bit is set to 1 from 0, the contents of the bits BPD1-0 are loaded into bit 1 and 0 (MOD2-0) of the Connection Memory HIGH. BPE (Begin Block Programming Enable) A zero to one transition of this bit enables the Connection Memory block programming feature delimited by the BPSA and BPEA registers as well as for a full block program. Once the BPE bit is set HIGH, the device will program the Connection Memory block as fast as than if the user manually programmed each Connection Memory location through the microprocessor. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE bit can be set to 0 to abort block programming. When RCML =1, all bits 14-0 in Connection Memory LOW will be reset to zero during block programming; when RCML = 0, bits 14-0 in Connection Memory LOW will retain their original values during block programming.
4
3
RCML (Reset Connection Memory LOW in Block Programming) OSB (Output Standby) MS1-0 (Memory Select)
2 1-0
When ODE = 0 and OSB = 0, the output drivers of transmit serial streams are in High-Impedance mode. When either ODE = 1 or OSB = 1, the output serial stream drivers function normally. These two bits decide which memory to be accessed via microprocessor port. 00 01 10 11 ----Connection Memory LOW Connection Memory HIGH Data Memory Reserved
9
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
MEMORY BLOCK PROGRAMMING The IDT72V73263 provides users with the capability of initializing the entire Connection Memory block in two frames. To set bits 2,1 and 0 of every Connection Memory HIGH location, set the Full Block Program to 1, write the desired pattern in to the Block Programming Data Bits (BPD 2). All of the block programming control can be found in the Control Register and enable the Block Program Enable bit. Enabled by setting the Block Program Enable bit of the Control Register HIGH. When the Block Programming Enable bit of the Control Register is set to HIGH, the Block Programming data will be loaded into the bits 2,1 and 0 of every Connection Memory HIGH location regardless of the selected data rate for the group. The Connection Memory LOW bits will be loaded with zeros when the Reset Connection Memory LOW(RCML) bit is enabled and is otherwise left untouched. When the memory block programming is complete, the device resets the Block Programming Enable and the BPD 2-0 bits to zero. The IDT72V73263 also incorporates a feature termed Group Block Programming. Group Block Programming, allows subsections of the Connection Memory to be block programmed as if the microprocessor were accessing the Connection Memory HIGH locations in a back-to-back fashion. The results in one connection memory high location being programmed for each C32i clock cycle. By having the TSI perform this function it allows the controlling
microprocessor more time to perform other functions. Also, the TSI can be more efficient in programming the locations since one CMH location is programmed every 32i clock cycles. The group block programming function programs "channel n" for all streams deliniated by the group before going to "channel n+1". A C-cycle representation is shown below. The Group Block Programming feature is composed of the Block Programming Start Address(BPSA), the Block Programming End Address(BPEA), and the BPE and BPD bits in the Control Register. The BPSA contains a start address for the block programming and BPEA contains an end address. The block programming will start at the start address and program until the end address even if the end address is "less" than the start address. In other words there is no mechanism to prevent a start address that is larger than the end address. If this occurs, the inverse CM locations in the given group are programmed resulting in a "wrap around" effect. This "wrap around" effect is independent for both the stream and channel addresses. This is illustrated in the Group Block Programming diagram See Figure 1 Group Block Programming Feature. Users must not initiat a block program too close (ahead) of the present transmit location. If this is done the TSI may simultaneously access the CM location that is being modified and unpredictable data on TX outputs may occur. It should be noted however, in order to enable the Group Block Programming the Full Block Program (FBP) must be 0.
10
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 4 BLOCK PROGRAMMING STARTING ADDRESS (BPSA) REGISTER
Reset Value:
15 0 14 G2
0000H
13 G1 12 G0 11 STA2 10 STA1 9 STA0 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0
BIT 15 14-12
NAME Unused G2-0 (Group Address bits 2-0) STA2-0 (Stream Address bits 2-0) CHA8-0 (Channel Address bits 8-0)
DESCRIPTION Must be zero for normal operation. These bits are used to select which group will be block programmed
11-9
These bits are used to select starting stream number for block programming.
8-0
These bits are used to select starting channel number for block programming.
TABLE 5 BLOCK PROGRAMMING ENDING ADDRESS (BPEA) REGISTER
Reset Value:
15 1 14 1
FFFFH
13 1 12 1 11 STA2 10 STA1 9 STA0 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0
BIT 15-12 11-9
NAME Unused STA2-0 (Stream Address bits 2-0) CHA8-0 (Channel Address bits 8-0)
DESCRIPTION Must be one for normal operation. These bits are used to select ending stream number for burst programming.
8-0
These bits are used to select starting channel number for burst programming.
11
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
CONNECTION MEMORY
Channels
INDUSTRIAL TEMPERATURE RANGE
CONNECTION MEMORY
Channels
0,0
X
X
255
0,0
X
X
255
X
Stream 2
X
X
X
Stream 2
X
Streams
X
X X
Streams
X X X X
X
X X
X
X
X
X
Stream 4
X
Stream 4
7 Channel 20
7
X
Channel 123
BPSA = St2, Ch20 BPEA = St4, Ch 123
Channel 20
X
Channel 123
BPSA = St4, Ch123 BPEA = St2, Ch20
0,0
X
Channels
X
255
0,0
X
Channels
X
255
X
X
X
Stream 2
X
Stream 2
X
Streams
X
X X
Streams
X X X
Stream 4
X
X X
X X
X
X
X
X
Stream 4
7 Channel 20
7
X
Channel 123
BPSA = ST4, CH20 BPEA = ST2, CH23
6140 drw04
Channel 20
X
Channel 123
BPSA = ST4, CH23 BPEA = ST2, CH20
6160 drw04
NOTE: The group number is defined by the stream address in the BPSA.
Figure 1. Group Block Programming
12
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
int ST, CH for (CH = StartChannel; CH <= EndChannel; CH++) { for (ST = StartStream; ST <= EndStream; ST++) { CMH[ST][CH] = BPD; }
} NOTE: This code is for illustraion purposes only. The IDT72V73263 is a HW instantiation of this kind of software.
Figure 2. "Basic Instantiation" /* GroupNum is 0-7 */ /* GroupDataRate = 2, 4, 8, 16. or 32 (2Mb/s, 4Mb/s, 8Mb/s, 16Mb/s, 32Mb/s) */ functional BlockProgram (int GroupNum; int GroupDataRate) { int ST, CH; int MaxStream = ((GroupNum * 8) + 7); int MaxChannel = (((GroupDataRate/2) * 32) - 1); /* StartChannel <= EndChannel */ if (StartChannel <= EndChannel){ for (CH = StartChannel; CH <= EndChannel; CH++){ /* StartStream <= EndStream and StartChannel <= EndChannel */ if (StartStream <= EndStream){ for (ST = StartStream; ST <= EndStream; ST++){ CMH[ST][CH] = BPD; } } /* StartStream > EndStream and StartChannel <= EndChannel */ else{ for (ST = EndStream; ST <= MaxStream; ST++){ CMH [ST] [CH] = BPD; } for (ST = (GroupNum*7); ST <= StartStream; ST++){ CMH [ST] [CH] = BPD; } } } } /* End > Start Channel */ else{ /* The last part to be programmed */ for (CH = EndChannel; CH <= MaxChannel; CH++){ /* StartStream > EndStream and StartChannel > EndChannel */ if (StartStream <= EndStream){ for (ST = StartStream; ST <= EndStream; ST++){ CMH [ST] [CH] = BPD; } } /* StartStream > EndStream and StartChannel > EndChannel */ else{ for (ST = EndStream; ST <= MaxStream; ST++){ CHM [ST] [CH] = BPD; } for (ST = GroupNum*7); ST <= StartStream; ST++){ CMH [ST] [CH] = BPD; } } ] /* The first part to be programmed */ for (CH = 0; CH <= StartChannel; CH++){ /* StartStream > EndStream and StartChannel > EndChannel */ if (StartStream <= EndStream){ for (ST = StartStream; ST <= EndStream; ST++){ CMH [ST] [CH] = BPD; } } /* StartStream > EndStream and StartChannel . EndChannel */ else{ for (ST = EndStream; ST <= MaxStream; ST++){ CMH [ST] [CH] = BPD; } for (ST = (GroupNum*7); ST <= StartStream; ST++){ CMH [ST] [CH] = BPD; } } } }
NOTE: This code is for illustration purposes only. The IDT72V73263 is a HW instantiation of this kind of software.
Figure 3. "Real" Instantiation of Memory Block Programming
13
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
BIT ERROR RATE
Pseudo-Random Bit Sequences (PRBS) can be independently transmitted and received. By setting the connection memory high bits to the BER transmit mode, that particular channel will transmit a BER pattern of the form 215-1. For the receiver only one channel can be specified and monitored at a given time. By setting the BER Input Selection (BIS) to a given channel, every error in the BER sequence will be incremented by one. If the more than 216-1 errors are encountered the BERR register will automatically overflow and be reset to zero. It is important to note that no interrupt or warning will be issued in this case. It is recommended that this register be
polled periodically and reset to prevent an overflow condition. To reset the Pseudo-random bit sequence and the error count registers set the PRST, CBER,and SBER,of the Control Register to high. See the Control Register for details. Following a write to the BERR register a read of the BERR will result in the present value of the BERR data. Likewise, when the Clear Bit Error Rate bit (CBER) in the control register is activated, this will clear the internal BERR (iBERR). As a general rule, a read of BERR should be proceeded by a write to BERR. Again, it should be noted that the write to the BERR register will actually initiate a transfer from the iBERR to the BERR while the microprocessor data is ignored.
TABLE 6 BER INPUT SELECTION REGISTER (BIS)
Reset Value:
15 0 14 BG2
Unknown (must be programmed)
13 BG1 12 BG0 11 BSA2 10 BSA1 9 BSA0 8 BCA8 7 BCA7 6 BCA6 5 BCA5 4 BCA4 3 BCA3 2 BCA2 1 BCA1 0 BCA0
BIT 15 14-12
NAME Unused BG2-BG0 (BER Input Group Address Bits) BSA2-BSA0 (BER Input Stream Address Bits)
DESCRIPTION Must be zero for normal operation These bits refer to the input data group which receives the BER data.
11-9
These bits refer to the input data stream which receives the BER data.
8-0
BCA8-BCA0 These bits refer to the input channel which receives the BER data. (Local BER Input Channel Address Bits)
TABLE 7 BIT ERROR RATE REGISTER (BERR)
Reset Value:
15 14
Unknown (must be programmed)
13 12 11 10 9 BER9 8 BER8 7 BER7 6 BER6 5 BER5 4 BER4 3 BER3 2 BER2 1 BER1 0 BER0
BER15 BER14 BER13 BER12 BER11 BER10
BIT 15-0
NAME BER15-BER0 (Local Bit Error Rate Count Bits)
DESCRIPTION These bits refer to the local bit error counts.
NOTE: Before a read of the BERR, a write to the BERR is neccesary. As a read only register the write will have no effect. See the Bit Error Rate section for more details.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment. Although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. Because data is often
delayed, this feature is useful in compensating for the skew between input streams. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5 clock periods forward with a resolution of 1/2 clock period, see Table 9. The output streams cannot be adjusted.
14
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 8 FRAME INPUT OFFSET REGISTER (FOR) BITS
Reset Value: Register FOR0 Register FOR1 Register FOR2 Register FOR3 Register FOR4 Register FOR5 Register FOR6 Register FOR7 Register FOR8 Register FOR9 Register FOR10 Register FOR11 Register FOR12 Register FOR13 Register FOR14 Register FOR15 Register NAME OFn2, OFn1, OFn0 (Offset Bits 2, 1 & 0) DLEn (Data Latch Edge) 0000H . 15 OF32 OF72 14 OF31 OF71 13 OF30 OF70 12 DLE3 DLE7 11 OF22 OF62 10 OF21 OF61 9 OF20 OF60 8 DLE2 DLE6 7 OF12 OF52 OF92 6 OF11 OF51 OF91 5 OF10 OF50 OF90 4 DLE1 DLE5 DLE9 3 OF02 OF42 OF82 2 OF01 OF41 OF81 1 OF00 OF40 OF80 0 DLE0 DLE4 DLE8
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 OF192 OF191 OF190 DLE19 OF182 OF181 OF180 DLE18 OF172 OF171 OF170 OF232 OF231 OF230 DLE23 OF222 OF221 OF220 DLE22 OF212 OF211 OF210 OF272 OF271 OF270 DLE27 OF262 OF261 OF260 DLE26 OF252 OF251 OF250 OF312 OF311 OF310 DLE31 OF302 OF301 OF300 DLE30 OF292 OF291 OF290 OF352 OF351 OF350 DLE35 OF342 OF341 OF340 DLE34 OF332 OF331 OF330 OF392 OF391 OF390 DLE39 OF382 OF381 OF380 DLE38 OF372 OF371 OF370 OF432 OF431 OF430 DLE43 OF422 OF421 OF420 DLE42 OF412 OF411 OF410 OF472 OF471 OF470 DLE47 OF462 OF461 OF460 DLE46 OF452 OF451 OF450 OF512 OF511 OF510 DLE51 OF502 OF501 OF500 DLE50 OF492 OF491 OF490 OF552 OF551 OF550 DLE55 OF542 OF541 OF540 DLE54 OF532 OF531 OF530 OF592 OF591 OF590 DLE59 OF582 OF581 OF580 DLE58 OF572 OF571 OF570 OF632 OF631 OF630 DLE63 OF622 OF621 OF620 DLE62 OF612 OF611 OF610 DESCRIPTION
DLE13 OF122 OF121 OF120 DLE12 DLE17 OD162 OD161 OF160 DLE16 DLE21 OF202 OF201 OF200 DLE20 DLE25 OF242 OF241 OF240 DLE24 DLE29 OF282 OF281 OF280 DLE28 DLE33 OF322 OF321 OF320 DLE32 DLE37 OF362 OF361 OF360 DLE36 DLE41 OF402 OF401 OF400 DLE40 DLE45 OF442 OF441 OF440 DLE44 DLE49 OF482 OF481 OF480 DLE48 DLE53 OF522 OF521 OF520 DLE52 DLE57 OF562 OF561 OF560 DLE56 DLE61 OF602 OF601 OF600 DLE60
These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame. The input frame offset can be selected to +7.5 clock periods from the point where the external frame pulse input signal is applied to the FOi input of the device. ST-BUS and GCI mode: DLEn = 0, offset is on the clock boundary. DLEn = 1, offset is a half cycle off of the clock boundary.
TABLE 9 OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELAY BITS (FD11, FD2-0)
INPUT STREAM OFFSET CLOCK PERIOD SHIFT BASED ON 32.768MHZ CLOCK 32.768Mb/s None + 0.5 + 1.0 + 1.5 + 2.0 + 2.5 + 3.0 + 3.5 + 7.5 16.384Mb/s None + 1.0 + 2.0 + 3.0 + 4.0 + 5.0 + 6.0 + 7.0 + 15.0 8.192Mb/s None + 1.0 + 2.0 + 3.0 + 4.0 + 5.0 + 6.0 + 7.0 + 15.0 4.096Mb/s None + 2.0 + 4.0 + 6.0 + 8.0 + 10.0 + 12.0 + 14.0 +30.0 2.048Mb/s None + 4.0 + 8.0 + 12.0 + 16.0 + 20.0 + 24.0 + 28.0
*********
CORRESPONDING OFFSET BITS OFn2 0 0 0 0 0 0 0 0 1 OFn1 0 0 0 0 1 1 1 1 1 OFn0 0 0 1 1 0 0 1 1 1 DLEn 0 1 0 1 0 1 0 1 1
+ 60.0
Examples for Input Offset Delay Timing 15
ST-BUS F32i
4MHz Clock
8MHz Clock
16MHz Clock
C32i
RX Stream @ 32Mb/s Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
Bit 6
offset = 0, DLE = 0
RX Stream @ 32Mb/s
Bit 7
offset = 1, DLE = 0
RX Stream @ 32Mb/s Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
offset = 1, DLE = 1
RX Stream @ 16Mb/s Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 7
offset = 0, DLE = 0
RX Stream @ 16Mb/s Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
offset = 1, DLE = 0
RX Stream @ 16Mb/s Bit 6 Bit 5 Bit 4
Bit 1
Bit 0
offset = 1, DLE = 1
RX Stream @ 8Mb/s Bit 7 Bit 6 Bit 5
Bit 7
Bit 3
offset = 0, DLE = 0
RX Stream @ 8Mb/s Bit 7 Bit 6
Bit 4
Bit 3
offset = 1, DLE = 0
RX Stream @ 8Mb/s Bit 7 Bit 6
Bit 5
Bit 4
offset = 1, DLE = 1
RX Stream @ 4Mb/s Bit 7 Bit 7
Bit 5
offset = 0, DLE = 0
RX Stream @ 4Mb/s
Bit 6 Bit 6
offset = 1, DLE = 0
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
16
Bit 7
RX Stream @ 4Mb/s
offset = 1, DLE = 1
RX Stream @ 2Mb/s
Bit 6
offset = 0, DLE = 0
RX Stream @ 2Mb/s
Bit 7
offset = 1, DLE = 0
RX Stream @ 2Mb/s
Bit 7
offset = 1, DLE = 1
6160 drw05
NOTE: denotes sample point of RX Data
INDUSTRIAL TEMPERATURE RANGE
Figure 4. ST-BUS Offset Timing
GCI BUS F32i
4MHz Clock
8MHz Clock
16MHz Clock
C32i
RX Stream @ 32Mb/s Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
Bit 6
offset = 0, DLE = 0
RX Stream @ 32Mb/s Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
offset = 1, DLE = 0
RX Stream @ 32Mb/s Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
offset = 1, DLE = 1
RX Stream @ 16Mb/s Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 7
offset = 0, DLE = 0
RX Stream @ 16Mb/s Bit 7 Bit 6 Bit 3 Bit 5 Bit 2 Bit 4
Bit 0
offset = 1, DLE = 0
RX Stream @ 16Mb/s Bit 4
Bit 1
Bit 0
offset = 1, DLE = 1
RX Stream @ 8Mb/s Bit 7 Bit 6 Bit 5 Bit 7 Bit 6 Bit 5
Bit 3
offset = 0, DLE = 0
RX Stream @ 8Mb/s Bit 7 Bit 6 Bit 5
Bit 4
offset = 1, DLE = 0
RX Stream @ 8Mb/s
Bit 4
offset = 1, DLE = 1
RX Stream @ 4Mb/s Bit 7 Bit 7
Bit 6
offset = 0, DLE = 0
RX Stream @ 4Mb/s Bit 7
Bit 6 Bit 6
offset = 1, DLE = 0
RX Stream @ 4Mb/s Bit 7
offset = 1, DLE = 1
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
17
RX Stream @ 2Mb/s
Bit 6
offset = 0, DLE = 0
RX Stream @ 2Mb/s
Bit 7
offset = 1, DLE = 0
RX Stream @ 2Mb/s
Bit 7
offset = 1, DLE = 1
6160 drw06
denotes sample point of RX data
Figure 5. GCI Offset Timing
INDUSTRIAL TEMPERATURE RANGE
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
OUTPUT ENABLE INDICATION The IDT72V73263 has the capability to indicate the state of the outputs (active or three-state) by enabling the Output Enable Indication in the DRSR. In the
Output Enable Indication mode however, those output streams cannot be used to transmit CM or DM data only OE data. In the diagram below notice how the transmitting stream, TX0 is uneffected by the enabling and disabling of the OE stream (TX8).
F32i
C32i
TX0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DS
Set OE1 = 0 in TDRSR0
Set OE1 = 1 in TDRSR0
TX8/OEI0 OEPOL = 1 TX8/OEI0 OEPOL = 0
6160 drw6a
NOTE: The TX0-7 pins are unaffected by the OEI Change.
Figure 6. The Effect of Enabling and Disabling of the OE Bit in TDRSR
18
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
F32i
1 2 3 4 5 6 7
INDUSTRIAL TEMPERATURE RANGE
8
C32i
TX0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TX8-OEI0 OEPOL =1 TX8-OEI0 OEPOL = 0
6160 drw6b
NOTE: Group 0 is in 32.768Mb/s and Group 1 is in OEI Mode.
Figure 7. OEI Function
F32i
C32i
TX0(-7)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DS
Set OE0 = 0 in TDRSR0 Set OE0 = 1 in TDRSR0
TX8-OEI0 OEPOL =1 TX8-OEI0 OEPOL = 0
6160 drw6c
NOTE: The OEI pins are unaffected by the OE0 change.
Figure 8. Group OE Operation
19
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 10 TRANSMIT DATA RATE SELECTION REGISTER (TDRSR)
Reset Value: TX DRSR 1
15 OE7 14 G72 13 G71 12 G70 11 OE6 10 G62 9 G61 8 G60 7 OE5 6 G52 5 G52 4 G51 3 OE4 2 G42 1 G41 0 G40
0000H
TX DRSR 0
15 OE3 14 G32 13 G31 12 G30 11 OE2 10 G22 9 G21 8 G20 7 OE1 6 G12 5 G11 4 G10 3 OE0 2 G02 1 G01 0 G00
OEx Gx2-Gx0
These bits can be used to High-Z the entire associated group. If OEx = 0 the group will be in High-Z. If OEx =1, the group is in Low-Z (active state). These three group bits are used to select the transmit data rates for the eight groups of eight streams. See table 11 for data rates. Gx2(1) 0 0 0 0 1 1 1 1 Gx1(1) 0 0 1 1 0 0 1 1 Gx0(1) 0 1 0 1 0 1 0 1 Data Rate 2.048Mb/s 4.096Mb/s 8.192Mb/s 16.384Mb/s 32.768Mb/s Reserved(2) Reserved(2) OEI(3)
If G0/G2/G4/G6 are programmed to be run at 32.768Mb/s, then G1/G3/G5/G7 will be unavailable, respectively, except for OEI purposes. In other words if G0 is programmed for 32.768Mb/s, G1 will only be available for OEI.
NOTES: 1. "x" corresponds to groups 0-7 (8 Data streams per group). 2. If the Gx2-0 are programmed to the reserved values the device will operate in the default 2.048Mb/s mode. 3. Only odd groups can be programmed for OEI. The OEI rate corresponds it's associated even group.
TABLE 11 TX GROUPING AND DATA RATES
GROUP NUMBER G0 G1 G2 G3 G4 G5 G6 G7 STREAMS 0-7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 SPEED 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s WITH OEI=1 2.048Mb/s-32.768Mb/s OEI<0-7> 2.048Mb/s-32.768Mb/s OEI<16-23> 2.048Mb/s-32.768Mb/s OEI<32-39> 2.048Mb/s-32.768Mb/s OEI<48-55>
20
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 12 RECEIVE DATA RATE SELECTION REGISTER(RDRSR)
Reset Value: RX DRSR 1
15 0 14 G72 13 G71 12 G70 11 0 10 G62 9 G61 8 G60 7 0 6 G52 5 G51 4 G50 3 0 2 G42 1 G41 0 G40
0000H
RX DRSR 0
15 0 14 G32 13 G31 12 G30 11 0 10 G22 9 G21 8 G20 7 0 6 G12 5 G11 4 G10 3 0 2 G02 1 G01 0 G00
Gx0-Gx2
These three group bits are used to select the receive data rates for the eight groups of eight streams. See table 13 for data rates. Gx2(1) 0 0 0 0 1 1 1 1 Gx1(1) 0 0 1 1 0 0 1 1 Gx0(1) 0 1 0 1 0 1 0 1 Data Rate 2.048Mb/s 4.096Mb/s 8.192Mb/s 16.384Mb/s 32.768Mb/s Reserved(2) Reserved(2) Reserved(2)
If G0/G2/G4/G6 are programmed to be run at 32.768Mb/s, then G1/G3/G5/G7 will be unavailable, respectively, except for OEI purposes. In other words if G0 is programmed for 32.768Mb/s, G1 will only be available for OEI.
NOTES: 1. "x" corresponds to groups 0-7 (8 Data streams per group). 2. If the Gx2-0 are programmed to the reserved values the device will operate in the default 2.048Mb/s mode. 3. Only odd groups can be programmed for OEI. The OEI rate corresponds to it's associated even group.
TABLE 13 RX GROUPING AND DATA RATES
GROUP NUMBER G0 G1 G2 G3 G4 G5 G6 G7 STREAMS 0-7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 SPEED 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s 2.048Mb/s-32.768Mb/s
21
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 14 CONNECTION MEMORY HIGH
Reset Value:
15 0 14 0
Unknown (must be programmed)
13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 MOD2 1 MOD1 0 MOD0
BIT 15-3 2-0
NAME Unused MOD2-0 MOD2 0 0 0 0 1 1 1 1
DESCRIPTION Must be zero for normal operation. MOD1 0 0 1 1 0 0 1 1 MOD0 0 1 0 1 0 1 0 1 MODE Variable Delay Mode Constant Delay Mode Reserved Reserved Processor Mode Bit Error Rate Test Reserved High-Impedance
TABLE 15 CONNECTION MEMORY LOW
Reset Value:
15 0 14 SAB5
Unknown (must be programmed)
13 SAB4 12 SAB3 11 SAB2 10 SAB1 9 SAB0 8 CAB8 7 CAB7 6 CAB6 5 CAB5 4 CAB4 3 CAB3 2 CAB2 1 CAB1 0 CAB0
BIT 15 14-9
NAME Unused SAB5-0 (Source Stream Address Bits) CAB8-0 (Source Channel Address Bits)
DESCRIPTION Must be zero for normal operation The binary value is the number of the data stream for the source of the connection.
8-0
The binary value is the number of the channel for the source of the connection.
NOTES: 1. When running the device at lower bit rates (i.e. 2, 4, 8, or 16.384Mb/s), make sure the bitscorresponding to the unused channels are set to 0. 2. When G0/G2/G4/G6 are programmed for 32.768Mb/s operation its corresponding group G1/G3/G5/F7 will be unavailable. 3. In processor mode, data in the lower byte (bits0-7) of the Connection Memory LOW will be output to the TX streams. The order in which the data are output will be starting from the LSB (Bit 0) to the MSB (Bit 7) of the lower byte. The figure below illustrates the sequence:
15
14
13
12
11
10
9
8
7 H
6 G
5 F
4 E
3 D
2 C
1 B
0 A
Figure 9. Processor Mode Bit Sequencing
22
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 16 BOUNDARY SCAN REGISTER BITS
Device Pin ODE RESET C32i F32i S/A DS CS R/W A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BEL DTA/BEH D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RX63 RX62 RX61 Boundary Scan Bit 0 to 267 Input Output Three-state Scan Cell Scan Cell Control 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 77 78 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 Device Pin RX60 RX59 RX58 RX57 RX56 TX63/OEI31 TX62/OEI30 TX61/OEI29 TX60/OEI28 TX59/OEI27 TX58/OEI26 TX57/OEI25 TX56/OEI24 TX55/OEi23 TX54/OEi22 TX53/OEI21 TX52/OEI20 TX51/OEI19 TX50/OEI18 TX49/OE17 TX48/OEI16 RX55 RX54 RX53 RX52 RX51 RX50 RX49 RX48 RX47 RX46 RX45 RX44 RX43 RX42 RX41 RX40 TX47/OEI15 TX46/OEI14 TX45/OEI13 TX44/OEI12 TX43/OEI11 TX42/OEI10 TX41/OEI9 TX40/OEI8 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 134 136 138 140 142 144 146 133 135 137 139 141 143 145 147 Input Scan Cell 79 80 81 82 83 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 Boundary Scan Bit 0 to 267 Output Three-state Scan Cell Control
23
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 16 BOUNDARY SCAN REGISTER BITS (CONTINUED)
Device Pin TX39/OEI7 TX38/OEI6 TX37/OEI5 TX36/OEI4 TX35/OEI3 TX34/OEI2 TX33/OEI1 TX32/OEI0 RX39 RX38 RX37 RX36 RX35 RX34 RX33 RX32 RX31 RX30 RX29 RX28 RX27 RX26 RX25 RX24 TX31 TX30 TX29 TX28 TX27 TX26 TX25 TX24 TX23 TX22 TX21 TX20 TX19 TX18 TX17 TX16 RX23 RX22 RX21 RX20 212 213 214 215 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 Input Scan Cell Boundary Scan Bit 0 to 267 Output Three-state Scan Cell Control 148 150 152 154 156 158 160 162 149 151 153 155 157 159 161 163 Device Pin RX19 RX18 RX17 RX16 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 260 261 262 263 264 265 266 267 Input Scan Cell 216 217 218 219 220 221 222 223 224 225 226 227 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259 Boundary Scan Bit 0 to 267 Output Three-state Scan Cell Control
24
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
JTAG SUPPORT
The IDT72V73263 JTAG interface conforms to the Boundary-Scan standard IEEE-1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. TEST ACCESS PORT (TAP) The Test Access Port (TAP) provides access to the test functions of the IDT72V73263. It consists of three input pins and one output pin. *Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. *Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VCC when it is not driven from an external source. *Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VCC when it is not driven from an external source. *Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out through the TDO pin on the falling edge of each TCK pulse. When no data is shifted through the boundary scan cells, the TDO driver is set to a High-Impedance state.
*Test Reset (TRST) Reset the JTAG scan structure. This pin is internally pulled to VCC when it is not driven from an external source. INSTRUCTION REGISTER In accordance with the IEEE-1149.1 standard, the IDT72V73263 uses public instructions. The IDT72V73263 JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shift-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. See Table 12 for Instruction decoding. TEST DATA REGISTER As specified in IEEE-1149.1, the IDT72V73263 JTAG Interface contains two test data registers: *The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the IDT72V73263 core logic. *The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO. The IDT72V73263 boundary scan register bits are shown in Table 14. Bit 0 is the first bit clocked out. All three-state enable bits are active HIGH. ID CODE REGISTER As specified in IEEE-1149.1, this instruction loads the IDR with the Revision Number, Device ID, JEDEC ID, and ID Register Indicator Bit. See Table 10.
TABLE 17 -- IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) VALUE 0x0 0x0430 0x33 1 Reserved for version number Defines IDT part number Allows unique identification of device vendor as IDT Indicates the presence of an ID register DESCRIPTION
TABLE 18 -- SCAN REGISTER SIZES
REGISTER NAME Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) BIT SIZE 4 1 32 Note(1)
NOTE: 1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative.
25
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
TABLE 19 -- SYSTEM INTERFACE PARAMETERS
INSTRUCTION EXTEST BYPASS IDCODE HIGH-Z SAMPLE/PRELOAD CODE 0000 1111 0010 0011 0001 DESCRIPTION Forces contents of the boundary scan cells onto the device outputs(1). Places the boundary scan register (BSR) between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs(2) and outputs(1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI.
RESERVED
All other codes Several combinations are reserved. Do not use other codes than those identified above.
NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS and TRST.
TABLE 20 -- JTAG AC ELECTRICAL CHARACTERISTICS (1,2,3,4)
SYMBOL tJCYC tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH PARAMETER JTAG Clock Input Period JTAG Clock HIGH JTAG Clock LOW JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold MIN. 100 40 40 50 50 0 15 15 MAX. 3(1) 3(1) 25 UNITS ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
tJCYC tJF TCK tJR tJCL tJCH
TDI/TMS (Device Inputs)(1) tJS TDO (Device Outputs) tJRSR TRST tJRST tJCD
6160 drw07
tJH tJDC
x
NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST.
Figure 10. JTAG Timing Specifications
26
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC Vi IO TS PD Parameter Supply Voltage Voltage on Digital Inputs Current at Digital Outputs Storage Temperature Package Power Dissapation Min. -0.5 GND -0.3 -50 -55 Max. +4.0 VCC +0.3 50 +125 2 Unit V V mA C W
RECOMMENDED OPERATING CONDITIONS(1)
Symbol VCC VIH(1) VIL TOP Parameter Positive Supply Input HIGH Voltage Input LOW Voltage Operating Temperature Industrial Min. 3.0 2.0 -0.3 -40 Typ. 3.3 25 Max. 3.6 VCC 0.8 +85 Unit V V V C
NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
NOTES: 1. Inputs/Outputs are not 5V tolerant 2. Voltages are with respect to ground (GND) unless otherwise stated.
DC ELECTRICAL CHARACTERISTICS
Symbol ICC IBL
(2)
Parameter Supply Current Input Leakage (input pins) Input Leakage (I/O pins) High-Impedance Leakage Output HIGH Voltage Output LOW Voltage
Min. -- -- 2.4
Typ.
Max. 380 60 60 60 0.4
Units mA A A A V V
IIL(3,4)
(3,4)
IOZ(3,4) VOH(5) VOL(6)
NOTES: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Outputs unloaded. 3. 0 V VCC. 4. Maximum leakage on pins (output or I/O pins in High-Impedance state) is over an applied voltage (V). 5. IOH = 10 mA. 6. IOL = 10 mA.
AC ELECTRICAL CHARACTERISTICS - TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS
Symbol VTT VHM VLM tr,tf Rating TTL Threshold TTL Rise/Fall Threshold Voltage HIGH TTL Rise/Fall Threshold Voltage LOW Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels CL(1) Output Load 50 1 Level 1.5 2.0 0.8 Unit V V V V ns V V pF
VDD
VDD 50 I/O Z0 = 50
N
Ch et Y ot
ara
riz cte
ed
6160 drw08
Figure 11. AC Termination
NOTE: 1. JTAG CL is 30pF
D.U.T.
330
N
27
Ch et Y ot
510
ara
riz cte
ed
30pF*
6160 drw09
Figure 12. AC Test Load
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - RESET AND ODE TIMING
Symbol tRZ tRS tODELZ Parameter Active to High-Z on Master Reset Reset Pulse Width Output Driver Enable (ODE) to Low-Z Min. -- 20 6 Typ. -- -- -- Max. 12 -- -- Units ns ns ns
RESET
tRZ tRS
TX
ODE
6160 Drw10
Figure 13. Reset and ODE Timing
AC ELECTRICAL CHARACTERISTICS - C32i AND ODE TO HIGH-Z TIMING AND C32i AND ODE TO LOW-Z TIMING
Symbol tCLZ
(1)
Parameter Clock to Low-Z Clock to High-Z ODE to Valid Data Output Driver Enable (ODE) to High-Z Outut Driver Enable (ODE) to Low-Z RX Hold Time Clock to Valid Data
Min. 3 -- 6 3 4 4 3
Typ. -- -- -- -- -- -- 7
Max. -- 9 -- 9 -- -- 9
Units ns ns ns ns ns ns ns
tCHZ(1) tODEA tODEHZ tODELZ tSIH(1) tSOD
NOTE: 1. CL = 30pF.
C32i
(ST-BUS mode)
C32i
(GCI mode)
tSOD tCHZ
ODE
tODEA tODELZ
tODEHZ
TX
VALID DATA
TX
tCLZ
VALID DATA
6160 drw12
TX
tSIH
VALID DATA
6160 drw11
Figure 14. Serial Output and External Control
28
Figure 15. Output Driver Enable (ODE)
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - ST-BUS TIMING
Symbol tCH tCL tCP tFPH tFPS tFPW tr,tf
(1)
Parameter C32i Pulse Width HIGH Clock rate = 32.768Mb/s C32i Pulse Width LOW Clock rate = 32.768Mb/s C32i Period Clock rate = 32.768Mb/s Frame Pulse Hold Time from C32i falling (ST-BUS or GCI) Frame Pulse Setup Time from C32i falling *ST-BUS or GCI) Frame Pulse Width (ST-BUS, GCI) Clock rate = 32.768Mb/s Clock Rise/Fall Time RX Hold Time RX Setup Time Clock to Valid Data
Min. 13 13 29 5 5 13 -- 4 2 3
Typ. 15.25 15.25 30.5 -- -- -- 1 -- -- 7
Max. 17 17 35 -- -- 31 -- -- -- 9
Units ns ns ns ns ns ns ns ns ns ns
tSIH tSIS tSOD
NOTE: 1. Parameters verified under test conditions.
F32i tr C32i tf
tFPW
tFPS
tFPH tSOD
tCH tCP
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
tCL
TX 32.768 Mb/s
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
tSIS RX 32.768 Mb/s
Bit 2 Bit 1 Bit 0 Bit 7
tSIH
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
tCH CLK-16.384 MHz(1) tSOD TX 16.384 Mb/s
Bit 1 Bit 0 Bit 7 Bit 6 Bit 5
tCL tCP
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
tSIS RX 16.384 Mb/s
Bit 1 Bit 0 Bit 7
tSIH
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
tSOD TX 8.192 Mb/s
Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
tSIS RX 8.192 Mb/s
Bit 0 Bit 7
tSIH
Bit 6 Bit 5 Bit 4
tCL CLK- 8.192 MHz(1) tSOD TX 4.096 Mb/s
Bit 0 Bit 7
tCH
tCP
Bit 6 Bit 5
tSIS RX 4.096 Mb/s
Bit 0 Bit 7
tSIH
Bit 6
CLK- 4.096 MHz(1)
tSOD TX 2.048 Mb/s
Bit 0 Bit 7 Bit 6
tSIS RX 2.048 Mb/s
Bit 7
tSIH
6160 drw13
NOTE: 1. These clocks are for reference purposes only. The TSI only accepts a 32.768MHz clock.
Figure 16. ST-BUS Timing
29
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - GCI BUS TIMING
Symbol tCH tCL tCP tFPH tFPS tFPW tr,tf
(1)
Parameter C32i Pulse Width HIGH Clock rate = 32.768Mb/s C32i Pulse Width Clock rate = 32.768Mb/s C32i Period Clock rate = 32.768Mb/s Frame Pulse Hold Time from C32i falling (ST-BUS or GCI) Frame Pulse Setup Time before C32i falling (ST-BUS or GCI) Frame Pulse Width (ST-BUS or GCI) Clock rate = 32.768Mb/s Clock Rise/Fall Time RX Hold Time RX Setup Time Clock to Valid Data
Min. 13 13 29 5 5 13 -- 4 2 3
Typ. 15.25 15.25 30.5 -- -- -- 1 -- -- 7
Max. 17 17 35 -- -- 31 -- -- -- 9
Units ns ns ns ns ns ns ns ns ns ns
tSIH tSIS tSOD
NOTE: 1. Parameters verified under test conditions.
tFPW F32i CLK- 32.768 MHz tSOD TX 32.768 Mb/s
Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3
tr
tf
tFPS
tFPH tCH tCP
Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
tCL
tSIS RX 32.768 Mb/s
Bit 6 Bit 7 Bit 0
tSIH
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
tCH CLK- 16.384 MHz(1) tSOD TX 16.384 Mb/s
Bit 6 Bit 7 Bit 0 Bit 1 Bit 2
tCL tCP
Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
tSIS RX 16.384 Mb/s
Bit 6 Bit 7 Bit 0
tSIH
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
tSOD TX 8.192 Mb/s
Bit 7 Bit 0 Bit 1 Bit 2 Bit 3
tSIS RX 8.192 Mb/s
Bit 7
tSIH
Bit 0 Bit 1 Bit 2 Bit 3
CLK- 8.192 MHz(1)
tCH
tCL
tSOD TX 4.096 Mb/s
Bit 7 Bit 0
tCP
Bit 1
tSIS RX 4.096 Mb/s
Bit 7 Bit 0
tSIH
Bit 1
CLK- 4.096 MHz(1)
tSOD TX 2.048 Mb/s
Bit 7 Bit 0
tSIS RX 2.048 Mb/s
Bit 0
tSIH
6160 drw14
NOTE: 1. These clocks are for reference purposes only. The TSI only accepts a 32.768MHz clock.
Figure 17. GCI Bus Timing
30
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - OEI BUS TIMING IN ST-BUS MODE
Symbol tCH tCHZ(2) tCL tCLZ(2) tCP tFPH tFPS tFPW tOEIE tOEID tr,tf(1) tSOD Parameter C32i Pulse Width HIGH Clock rate = 32.768Mb/s Clock to High-Z C32i Pulse Width Clock rate = 32.768Mb/s Clock to Low-Z C32i Period Clock rate = 32.768Mb/s Frame Pulse Hold Time from C32i falling (ST-BUS or GCI) Frame Pulse Setup Time before C32i falling (ST-BUS or GCI) Frame Pulse Width (ST-BUS or GCI) Clock rate = 32.768Mb/s Clock to OEI Enable Clock to OEI Disable Clock Rise/Fall Time Clock to Valid Data
Min. 13 -- 13 3 29 5 5 13 3 3 -- 3
Typ. 15.25 -- 15.25 -- 30.5 -- -- -- -- -- 1 7
Max. 17 9 17 -- 35 -- -- 31 9 9 -- 9
Units ns ns ns ns ns ns ns ns ns ns ns ns
NOTE: 1. Parameters verified under test conditions. 2. CL = 300pF
F32i tFPS C32i
tFPW tFPH tCH tCL tr tf
tCP
tSOD TX16.384 Mb/s tCLZ tOEIE OEI(1) OEI(2) tOEIE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
tCHZ
tOEID
tOEID
6160 drw15
NOTES: 1) OEPOL = 1 2) OEPOL = 0
Figure 18. OEI Bus Timing in ST-BUS Mode
31
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - RX TO TX INTERNAL BYPASS BIT
SYMBOL tBC PARAMETER MIN. 2 TYP. 8 MAX. 12 UNITS ns
RX tBC tBC TX tBC
6160 drw16
tBC = end to end chip delay
Figure 19. RX to TX Internal Bypass Bit
32
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - MOTOROLA NON-MULTIPLEXED BUS ASYCHRONOUS TIMING MEMORY ACCESS
SYMBOL tADH tADS tAKD(1) tAKH
(1,2,3)
PARAMETER Address Hold after DS Rising Address Setup from DS Falling Acknowledgment Delay: Reading/Writing Memory Acknowledgment Hold Time CS Hold Time after DS Rising CS Setup from DS Falling Data Setup from DTA LOW on Read Data Hold On Read Data Hold on Read Data Strobe Setup Time Data Strobe on Write R/W Hold after DS Rising R/W Setup from DS Falling Valid Data Delay on Write
MIN. 2 2 -- -- 0 0 2 10 5 2 6 3 3 2
TYP. -- -- -- -- -- -- -- 15 -- -- -- -- -- --
MAX. -- -- 30 10 -- -- -- 25 -- -- -- -- -- --
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCSH tCSS tDDR
(1)
tDHR(1) tDHW tDSS tDSPW tRWH tRWS tSWD NOTES: 1. CL = 30pF 2. RL = 1K
3. High-Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 4. To achieve on clock cycle fast memory access, this setup time, tDSS should be met. Otherwise, worst-case memory access operation is determined by tAKD.
CLK GCI
CLK ST-BUS tDSS DS tCSS CS tRWS R/W tADH VALID WRITE ADDRESS tSWD D0-D15 VALID WRITE DATA tDHW tADS VALID READ ADDRESS tDHR VALID READ DATA tDDR tAKD DTA 6160 drw17 tAKH tAKD tAKH tADH tRWH tRWS tRWH tCSH tCSS tCSH tDSPW tDSS
tADS A0-A15
Figure 20. Motorola Non-Multiplexed Bus Asychronous Memory Access
33
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - MOTOROLA NON-MULTIPLEXED BUS ASYNCRONOUS TIMING REGISTER ACCESS
SYMBOL tADH tADS tAKD(1) tAKH
(1,2,3)
PARAMETER Address Hold after DS Rising Address Setup from DS Falling Acknowledgment Delay: Reading/Writing Registers Acknowledgment Hold Time CS Hold Time after DS Rising CS Setup from DS Falling Data Setup from DTA LOW on Read Data Hold On Read Data Hold on Read Data Strobe on Write Data Setup on Write R/W Hold after DS Rising R/W Setup from DS Falling
MIN. 2 2 -- -- 0 0 2 10 5 6 10 3 3
TYP. -- -- -- -- -- -- -- 15 -- -- -- -- --
MAX. -- -- 40 20 -- -- -- 25 -- -- -- -- --
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
tCSH tCSS tDDR
(1)
tDHR(1) tDHW tDSPW tDSW tRWH tSWD NOTES: 1. CL = 30pF 2. RL = 1K
3. High-Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 4. To achieve on clock cycle fast memory access, this setup time, tDSS should be met. Otherwise, worst-case memory access operation is determined by tAKD.
DS tCSS CS tRWS R/W tADH VALID WRITE ADDRESS tDSW tDHW VALID WRITE DATA tAKD DTA 6160 drw17a tAKH tADS VALID READ ADDRESS tDHR VALID READ DATA tDDR tAKD tAKH tADH tRWH tRWS tRWH tCSH tDSPW tCSS tCSH
tADS A0-A15
D0-D15
Figure 21. Motorola Non-Multiplexed Bus Asychronous Timing Register Access
34
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - SYNCHRONOUS BUS TIMING
SYMBOL tADH tADS tBEH tBES tCD tDHR(1,2,3) tDHW tDSW tRWH tRWS tsCSH tsCSS NOTES: 1. CL = 30pF 2. RL = 1K 3. High-Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 4. To achieve on clock cycle fast memory access, this setup time, tDSS should be met. Otherwise, worst-case memory access operation is determined by tAKD. PARAMETER Address Hold Address Setup Byte Enable Hold Btye Enable Setup Clock to Data Data Hold on Read Data Hold on Write Data Setup on Write R/W Hold R/W Setup CS Hold CS Setup MIN. 3 3 3 3 -- 10 3 3 3 3 3 3 TYP. -- -- -- -- -- 15 -- -- -- -- -- -- MAX. -- -- -- -- 20 25 -- -- -- -- -- -- UNITS ns ns ns ns ns ns ns ns ns ns ns ns
CLK ST-BUS
CLK GCI tSCSS CS tSCSH tSCSS tSCSH
tBES BEN
tBEH
tBES
tBEH
tRWS R/W tRWS tRWH
tRWH
tADS A0-15 READ
tADH
tADS WRITE
tADH
tDSW tDHW DATA-IN Dn
tCD DATA-OUT Qn
tDHR
6160 drw18
Figure 22. Synchronous Bus Timing
35
IDT72V73263 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 16,384 x 16,384 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - BYTE ENABLE
SYMBOL tADH tADS tBEH tBES tCD tDHR
(1)
PARAMETER Address Hold Address Setup Byte Enable Hold Byte Enable Setup Clock to Data Data Hold on Read R/W Hold R/W Setup CS Hold CS Setup
MIN. 3 3 3 3 -- 10 3 3 3 3
TYP. -- -- -- -- -- 15 -- -- -- --
MAX. -- -- -- -- 20 25 -- -- -- --
UNITS ns ns ns ns ns ns ns ns ns ns
tRWH tRWS tsCSH tsCSS NOTES: 1. CL = 30pF 2. RL = 1K
3. High-Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
CLK ST-BUS
CLK GCI tSCSS CS tSCSH tSCSS tSCSH
tBES BEL
tBEH
tBES BEH
tBEH
R/W tRWS tRWH
tRWS
tRWH
A0-15(3)
READ tADS tADS tADH
READ tADH
D0-7 tCD
D0-7 tCD tDHR tDHR
D8-15
D8-15
6160 drw19
Figure 23. Byte Enable
36
ORDERING INFORMATION
IDT XXXXXX Device Type XX Package X Process/ Temperature Range BLANK Commercial (-40C to +85C)
BB DR
Plastic Ball Grid Array (PBGA, BB208-1) Plastic Quad Flatpack (PQFP, DR208-1)
72V73263
16.384 x 16.384 3.3V Time Slot Interchange Digital Switch with Rate Matching
6160 drw22
DATASHEET DOCUMENT HISTORY
06/30/2003 09/08/2003 10/28/2003 pgs. 9,14 and 33. pgs. 1, 4, 5, 20, 28, 33 and 34. pg. 1 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
37
for Tech Support: 408-330-1753 email: TELECOMhelp@idt.com

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